Available upon request
I am currently working on my PhD in Electrical Engineering at UCLA (started Fall '05). I received an MS in May, 2002 from the department of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. I received a B.S. in Electrical Engineering with a minor in Mathematics from the University of Alaska Fairbanks in the Spring of '99.
Research
My PhD research is in the area of FPGA fault-tolerance in the Embedded Computing Systems division of the Electrical Engineering Dept. at UCLA. My advisor is Dr. Lei He.
My ECE Masters research work was in the Center for Reliable and High Performance Computing at UIUC and involved host-based testing of emerging non-volatile RAM technology (FRAM among others) using an FPGA to perform reliability and endurance tests. The project involved developing and choosing appropriate test algorithms for the new memory, programming an FPGA and designing and building supporting circuitry to form a testbed for the memory, and conducting preliminary tests with the completed testbed. This project was funded by NASA's Jet Propulsion Lab (JPL) in order to determine the suitability of these new RAMs for use in deep space missions. The reliability and endurance characterization involved new test algorithms aimed at non-volatile memories, as well as very-low-voltage (VLV) testing. My advisor was Dr. Janak Patel.
Coursework at U of I (see resume for undergrad coursework)
MATH 314: Linear Algebra
CS 110: C++ Programming
ECE 325: VLSI System Design
ECE 348: Intro to Artificial Intelligence
ECE 382: Large Scale Integrated Circuit Design
ECE 412: Advanced Computer Architecture
ECE 415: Control System Theory and Design
ECE 442: Fault Tolerant Systems
GE 495: Evaluation and Management of Engineering Design Projects
Seminars at U of I
ECE 400: ECE Graduate Seminar
ECE 490X: Computer Engineering Seminar
Publications
V. M. Rao, J. Patel, J. Patel, J. Namkung. An FPGA-Based Testbed for Reliability and Endurance Characterization of Non-Volatile Memory , in Proceedings of the 2001 Non-Volatile Memory Symposium, San Diego, California, 2001.
V.M. Rao, An FPGA-Based Testbed for Reliability and Endurance Characterization of Nonvolatile Memories, M.S. Thesis, University of Illinois at Urbana-Champaign, May 2002. (Download as ZIP-Compressed File)
Projects while at University of Illinois at Urbana-Champaign
- Project titled "Implementation of 4-Bit AMD2901 Microprocessor" which included design, simulation, and entire layout using Cadence tools
- Project titled "Implementation of 8-bit Accumulator" which included design, simulation and entire layout using Mentor Graphics tools. Design met 500 MHz speed specification as well as area, power specifications
- Project titled "A Survey of Hardware and Software Distributed Shared Memory Systems"
- Project titled "User Customizable Automatic Level Control for Audio Applications Using the Motorola 68HC11 Microcontroller and MATLAB
Awards while at University of Illinois at Urbana-Champaign
- NASA "New Technology Report" Award (Fall 2001)
- GTE Fellowship (Fall 1999-Spring 2000)
- 50% Research Assistantship (Spring 2001-Spring 2002)
- 25% Teaching Assistantship / 25% Research Assistantship (Fall 2000)
- 50% Teaching Assistantship (Fall 1999-Spring 2000)
- Voted by students as one of two "Excellent Teaching Assistants" (TAs) for the course ECE110 (along with co-TA Amit Pandey) for 2 consecutive semesters (Fall 1999 and Spring 2000)
